1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, such as CPUs including scaled transistor elements, and particularly to performance reducing charge trap creation at the interface between the gate dielectric material and the channel region.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles, to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, silicon dioxide is preferably used in field effect transistors as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may represent limitations for performance driven circuits. That is, product reliability and lifetime are strongly correlated with short channel effects, i.e., impact ionization and hot carrier injection (HCI) in combination with gate dielectric leakage.
A further long-known effect may increasingly play an important role for CMOS devices, as threshold voltages and supply voltages are steadily reduced. It was observed in the 1960s that application of a negative voltage, possibly in combination with thermal stress, to the gate electrode of MOS transistors may result in a shift of the threshold voltage, i.e., a shift of the specific gate voltage at which a conductive channel forms adjacent to the gate insulation layer. This effect, also referred to as “negative bias temperature instability (NBTI),” is mainly present in PMOS transistors and was not considered particularly relevant for semiconductor devices in the following years due to the low influence on the overall device performance of devices, in particular as NMOS devices have increasingly been developed. This situation changed with the introduction of complex CMOS devices including high performance logic circuits, in which millions of signal nodes with PMOS and NMOS transistors are typically provided. As explained above, in these devices, the threshold voltage and the supply voltages have been reduced, while, on the other hand, the electric fields across the gate dielectrics is increased. Under such conditions, a change of the threshold voltage may have an even higher impact, since transistor operation variability may increase due to relatively higher influence of a shift of the threshold voltage. Moreover, the operating states resulting in the application of a negative voltage to the gate electrode of a PMOS transistor may depend on the signal path considered and the overall operational conditions, thereby making the threshold shift highly non-predictable and hence requiring appropriately set design criteria to ensure the desired performance of the transistors over the entire specified lifetime of the device. For example, a shift of the threshold voltage over the accumulated operating time may finally lead to violation of the timing specification of the device, which may not allow further use of the device despite the fact that no other major failure has occurred.
Generally, the NBTI effect is associated with the quality of the gate dielectric, for instance comprising silicon, oxygen and nitrogen, and also the quality of the interface between the silicon in the channel region and the gate dielectric. That is, upon a negative gate voltage, elevated temperature and other stress conditions, a charge trap may be created in the vicinity of the interface, thereby causing holes to be trapped. Due to the localized positive interface states and the trapped charges, a shift in threshold voltage may be observed that may increase over time depending on the overall stress conditions experienced by the transistors. In NMOS transistors, this effect is significantly less pronounced, since the interface states and the fixed charges are of opposite polarity, thereby resulting in a lower performance degrading net effect.
For this reason, it is important in advanced applications to appropriately select the characteristics of the gate dielectric material with respect to material composition and thickness in order to maintain hot carrier injection and NBTI effects at an acceptable level, especially for P-channel transistors. Due to the reduced design flexibility and less pronounced enhancement of device performance for semiconductor devices requiring highly scaled gate dielectric thickness values and also overall device dimensions, the present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.